Palladium Z3 and Protium X3 Standard Design Compile Flow

Palladium Z3 Compile Flow:

1. Design Analysis and Compilation:

• Use vlan and vhan commands to analyze VHDL and Verilog parts separately
• Compile the entire design using the ixcom command to generate the simulation snapshot

2. Multi-Step Compilation with xrun:

• Compile and elaborate the design using xrun -hw -compile and xrun -hw -elaborate commands
• The -hw option enables compilation for SA (Simulation Acceleration) mode and internally invokes IXCOM tools (vlan, vhan)
• Simulate and debug using xrun -R or xrun -R -xedebug

3. IXCOM Compilation Process:

• Software Simulation Mode: Complete design runs on xrun simulator
• Simulation Acceleration Mode: One part runs on xrun simulator, other part runs on emulator
• IXCOM invokes tools for: source analysis and design elaboration, source transformation and code generation, writing design information to databases
• In SA mode, IXCOM also invokes back-end compilers to generate emulator configuration data

4. ICE Compilation Flow:

• Converts design into compilation database that can be downloaded to the emulator
• Uses XEL commands, UNIX commands, and input/output files to import, check, and compile design

Protium X3 Compile Flow:

1. Similar Front-End Compilation:

• Protium X3 shares a front-end Palladium compiler for guaranteed congruent behavior
• Similar compile step like Palladium prior to FPGA implementation

2. Two Compilation Options:

• Option 1: Use hdl* commands defined in compile script file (e.g., compile.qel) and xeCompile for RTL compile and synthesis
• Option 2: Use vavlog/vaelab commands to accomplish the same as Option 1

Key Tools:

• xrun: Compiling and running designs in SA mode
• IXCOM: Main compiler for generating simulation snapshots
• ICE: In-circuit emulation compilation flow
• vlan/vhan: Analyze Verilog and VHDL files

Note: You don’t feed RTL directly - the tools process your RTL through these compilation stages to create the runnable emulator image.